Who needs accelerators when you have 192 cores? Pictured: AMD 5th Gen EPYC "Turin".

AMD's upcoming server processor, the 5th Gen EPYC "Turin," has been captured in images as an engineering sample and is likely being evaluated by the company's data-center or cloud customers. The processor boasts an impressive core-count of 192-core/384-thread in its high-density cloud-focused variant, utilizing "Zen 5c" CPU cores. The regular version, which utilizes larger "Zen 5" cores capable of sustaining higher clock speeds, features a respectable core-count of 128-core/256-thread, an increase from the 96-core/192-thread of the "Zen 4" based EPYC "Genoa."

The EPYC "Turin" server processor, based on "Zen 5," includes an updated sIOD (server I/O die) surrounded by up to 16 CCDs (CPU complex dies). AMD is expected to manufacture these CCDs on the TSMC N4P foundry node, which is an advanced version of the TSMC N4 node currently used for its "Phoenix" client processors, and the TSMC N5 node used for its "Zen 4" CCD. TSMC claims that the N4P node offers up to a 22% improvement in power efficiency over N5, as well as a 6% increase in transistor density. Each of the "Zen 5" CCDs is confirmed to have 8 CPU cores sharing a 32 MB L3 cache memory. With 16 CCDs, the processor achieves a core-count of 128-core/256-thread. The high-density "Turin," designed for cloud data-centers, is a different beast altogether.

The high-density "Turin" processor utilizes 12 "Zen 5c" CCDs. Similar to "Zen 4c" in relation to "Zen 4," the "Zen 5c" is a physically compacted version of the larger "Zen 5" core, maintaining the same ISA (instruction sets) and IPC, but typically operating at lower clock speeds than the regular "Zen 5" cores. It is intended for high core-count processors. The high-density "Turin" MCM (multi-chip module) features the same sIOD as the regular "Turin," but with 12 "Zen 5c" CCDs. Each CCD contains 16 "Zen 5c" cores sharing a 32 MB L3 cache. Notably, the current "Zen 4c" CCD has two CCX (CPU core complexes), with each containing 8 "Zen 4c" cores sharing a 16 MB L3 cache. The "Zen 5c" CCD doubles the total addressable L3 cache.