AMD Zen 6 Processors to Adopt Split-Node Manufacturing Strategy
AMD is set to introduce a significant architectural shift with its upcoming "Zen 6" desktop Ryzen and server EPYC processors. The company will implement a split-node manufacturing approach, leveraging TSMC’s advanced process technologies to optimize both performance and efficiency. In this new design, the CPU core complex die (CCD) will be fabricated using TSMC’s N2P 2 nm node, while the I/O die (IOD) will utilize the N3P 3 nm node.
Production Timeline and Node Advantages
TSMC is expected to begin volume production of its 2 nm node around the third quarter of 2026. This timeline positions AMD to potentially launch limited shipments of Zen 6 processors as early as late Q3 2026, with broader availability anticipated in the fourth quarter. By adopting a split-node strategy, AMD can allocate the cutting-edge N2P process to the compute chiplet—where performance gains are most critical—while using the more cost-effective N3P node for the IOD, which handles non-core functions.
Zen 6 Architecture and Core Configuration
The Zen 6 compute chiplet will integrate the next-generation cores alongside a significantly expanded shared L3 cache. According to early reports, each CCD may feature 12 Zen 6 cores with simultaneous multithreading (SMT) support, and a shared L3 cache potentially increasing to around 48 MB per CCD—an improvement over previous generations. Consumer desktop CPUs are expected to combine up to two CCDs with a single IOD, resulting in configurations of up to 24 cores and 48 threads. Server-class EPYC processors will scale even further, depending on packaging and platform requirements.
Performance and Platform Compatibility
Zen 6 processors are targeting double-digit improvements in instructions per clock (IPC), higher sustained clock speeds, and enhanced power efficiency, all enabled by the advanced 2 nm and 3 nm process nodes. The use of N3P for the IOD helps manage costs for non-core logic, while the N2P node is reserved for the compute die to maximize generational performance gains. Despite the premium associated with the latest TSMC nodes, this selective approach balances performance and cost-effectiveness.
Importantly, Zen 6 will maintain compatibility with the existing AM5 socket, allowing users to upgrade their CPUs without needing a complete platform overhaul. This ensures a smoother transition for enthusiasts and professionals looking to adopt the new architecture.
EPYC "Venice" and Datacenter Innovations
For datacenter applications, the EPYC "Venice" generation based on Zen 6 will introduce a server-specific I/O die (sIOD) that supports PCIe Gen 6. This advancement doubles bandwidth for GPUs, SSDs, and network interface cards, addressing the growing demands of high-performance computing environments. AMD is also projecting memory bandwidth capabilities of up to 1.6 TB/s for these CPUs, with the potential for some of these improvements to benefit future consumer platforms as well.
With the Zen 6 family, AMD is poised to deliver substantial advancements in CPU performance, efficiency, and scalability, leveraging the latest semiconductor technologies to meet the evolving needs of both desktop and server markets.
