Hot Chips 2025: NVIDIA Unveils Grace Blackwell Superchip
During Hot Chips 2025, NVIDIA showcased the GB10 "Grace Blackwell" superchip, featuring a compact multi-die design aimed at bringing datacenter capabilities to a desktop-sized workstation. This chip combines a MediaTek-sourced Arm CPU die with a Blackwell GPU die in a 2.5D package manufactured using TSMC's 3 nm process.
The CPU component consists of 20 Arm v9.2 cores divided into two clusters of ten, each cluster supported by a 16 MB shared L3 cache (32 MB total), with each core having its private L2 cache. The memory system utilizes a unified LPDDR5X-9400 fabric on a 256-bit bus, offering support for up to 128 GB of memory and delivering approximately 301 GB/s of raw bandwidth to the package.
On the GPU side, NVIDIA described the die as a scaled Blackwell configuration optimized for low-power, small-form-factor operation. The GPU boasts a peak throughput of around 31 TeraFLOPS for FP32 and approximately 1,000 TOPS with NVIDIA's NVFP4 reduced-precision format. It includes a large 24 MB L2 cache that can function as a higher-level cache visible to the CPU, establishing a coherent cache hierarchy between the two dies.
NVIDIA highlighted that the inter-die C2C link provides aggregate bandwidth of about 600 GB/s, facilitating low-latency sharing without the need for extensive software-managed copying. The superchip is rated at around 140 W TDP and offers multi-display outputs, security features, and virtualization capabilities tailored for professional workloads.
NVIDIA positioned DGX Spark as a "gateway" workstation running DGX Base OS and the company's AI stack locally, with the ability to scale workloads to larger DGX systems or cloud hosts as required. The vendor has set a reference price of $3,999 for the GB10 SoC, which is paving the way for consumer-grade N1/N1x SoC that is expected to feature a similar GPU and CPU configuration.
The computing power of the GB10 SoC superchip is deemed sufficient for a consumer laptop, prompting anticipation for NVIDIA's plans regarding the N1/N1x chips.